Memory address generation in programmable logic array devices

Abstract

A programmable logic array integrated circuit device has a relatively large block 20 of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, an address decoder 36 normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter 40 or other similar coded address signal generating circuitry is used to supply address information to the decoder 36.

Claims

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (0)

    Publication numberPublication dateAssigneeTitle

NO-Patent Citations (0)

    Title

Cited By (2)

    Publication numberPublication dateAssigneeTitle
    GB-2313459-BMay 03, 2000Chip ExpressCustomizable integrated circuit devices
    US-6348669-B1February 19, 2002Jenact LimitedRF/microwave energized plasma light source