Data processing apparatus registers

Abstract

A data processing system is provided including an arithmetic logic unit 20, 22, 24 receiving input operands from M X-bit registers 10 to produce output data words stored within N Y-bit registers 10, where M/N = 3, 8 * less than or equal to * Y-X * less than or equal to * 16 and 3X = 2Y. This arrangement is particularly suited for digital signal processing and in situations where each input operand is used a plurality of times before a new input operand is loaded in its place in a register.

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Cited By (2)

    Publication numberPublication dateAssigneeTitle
    US-6314443-B1November 06, 2001Arm LimitedDouble/saturate/add/saturate and double/saturate/subtract/saturate operations in a data processing system
    WO-0031621-A1June 02, 2000Arm LimitedOperations arithmetiques dans un systeme de traitement de donnees